Caches are conventionally used to improve processor core performance in systems where the data accessed by the processor core is located in slow and/or far memory (i.e., double data rate 3 memory). A usual cache strategy is to bring a line of data on any data request from the processor core that causes a cache miss and store the line of data in the local cache memory. A subsequent accesses to the same line is handled by the cache and the local cache memory is accessed.
Simultaneous accesses to the same bank in the local cache memory cause conflicts. Stalls in the processor cores are created by the conflicts in the cache. The stalls cause degradations in application cycle counts.
It would be desirable to implement a memory conflicts learning capability.